Well, the answer to this question mostly depends on what kind of implementation you choose for your multiple-input 32-bit wide adders (there are several different solutions to this speed versus gate count trade-off). Usually, when using the term "gate equivalent," engineers are talking about FPGAs, where it is a cool marketing slogan that tries to persuade you that the FPGA is much more powerful that you'd think from its number of logical elements because some of them can implement complicated circuits that would need a high number of gates otherwise. In this case, you will almost certainly use whatever special provisions your FPGA chip has for wide additions (and your GE count will depend on whatever its manufacturer's marketting department believes to get away with for translating that into "typical" gate counts of comparable circuits).
If your goal is to estimate how much of SHA256 you can fit into a given FPGA, you may be even better off comparing with what others have achieved. This may take a bit of digging, but will give you good estimates. The FPGA section of this wiki page for mining hardware comparison could give you initial links. I don't have numbers at the ready, but I remember having concluded ca. 15 month ago that those FPGAs that were mature enough then to have single-unit bare chip retail prices around 100 $ (the most computing per money you could get then) tended to be just about big enough for a fully unrolled and fully pipelined double-SHA256 implementation.