System on a chip

A system on a chip or system on chip (SoC) is an integrated circuit (also known as an "IC" or "chip") that integrates all components of a computer or other electronic systems. These components typically include a central processing unit (CPU), memory, input/output ports and secondary storage all on a single substrate. It may contain digital, analog, mixed-signal, and often radio-frequency functions, depending on the application. SoCs are very common in the mobile computing market because of their low power consumption.[1] SoCs are commonly applied in the area of embedded systems.

Systems on Chip are in contrast to the common traditional motherboard-based PC architecture, which separates components based on function and connects them through a central interfacing circuit board, so-termed a "mother board". Whereas a motherboard houses or connects detachable or replaceable components such as a CPU, graphics and memory interfaces, hard-disk and USB connectivity, memories (both random access and read only) and secondary storage; SoCs integrate all of these components into a single integrated circuit, as if all these functions were built into the motherboard. More integrated hardware designs improve performance and reduce power consumption and semiconductor die area needed for an equivalent design at the cost of reduced modularity and replaceability of components, and SoC designs are by definition fully or nearly fully integrated across different components. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets.

An SoC integrates a microcontroller (or microprocessor) with advanced peripherals like graphics processing unit (GPU), Wi-Fi module, or coprocessor. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with such advanced peripherals.

In general, there are three distinguishable types of SoCs: SoCs built around a microcontroller; SoCs built around a microprocessor (often found in mobile phones); and specialized SoCs designed for specific applications that do not fit into the above two categories. A separate category may be Programmable SoC (PSoC), where some of the internal elements can be programmable in a manner analogous to a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD).


A typical SoC consists of:

A computer bus connects the different components, also called "blocks" of the System-on-Chip. Direct memory access controllers route data directly between external interfaces and memory, bypassing the CPU or control unit, thereby increasing the data throughput (the amount of data processed per time) of the SoC.

Design flow

An SoC consists of both the hardware, described above, and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software at the same time.

Most SoCs are developed from pre-qualified hardware component specifications for the hardware elements or "blocks" described above, together with software device drivers that may control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using computer aided design tools; the software modules are integrated using a software-development environment.

Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract hardware description language termed register transfer level (RTL) which defines the circuit behavior. These elements are connected together in the hardware description language to create the full SoC design.

Chips are verified for logical correctness before being sent to foundry. This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle, often quoted as 70%.[2] With the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and OpenVera are being used. Bugs found in the verification stage are reported to the designer.

Traditionally, engineers have employed simulation acceleration, emulation or prototyping on a reprogrammable hardware device (FPGA) to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as tape-out.

With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.

FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system’s full operating frequency with real-world stimuli. Tools such as Certus[3] are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.

In parallel, the hardware elements are grouped and passed through a process of logic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a netlist describing the design as a physical circuit and its interconnections. These netlists are combined with the glue logic connecting the components to produce the schematic description of the SoC as a circuit which can be printed onto a chip.


The netlists described above are used as the basis for the physical design (place and route) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.

When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.

SoCs can be fabricated by several technologies, including:

SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well.

However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher non-recurring engineering costs.

When it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.[4]


SoC research and development often compares many options. Benchmarks, such as COSMIC,[5] are developed to help such evaluations.

See also


  1. Pete Bennett, EE Times. "The why, where and what of low-power SoC design." December 2, 2004. Retrieved July 28, 2015.
  2. EE Times. "Is verification really 70 percent?." June 14, 2004. Retrieved July 28, 2015.
  3. Brian Bailey, EE Times. "Tektronix hopes to shake up ASIC prototyping." October 30, 2012. Retrieved July 28, 2015.
  4. EE Times. "The Great Debate: SOC vs. SIP." March 21, 2005. Retrieved July 28, 2015.
  5. "COSMIC Heterogeneous Multiprocessor Benchmark Suite"

Further reading

  • SOCC Annual IEEE International SOC Conference
  • Baya free SoC platform assembly and IP integration tool
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